The CompactPCI backplane is based on the (parallel) PCI bus. The ExpressCard
however, as well as its pendant PCI Express Mini Card, requires a (serial)
PCI Express l/F. In addition, both card types may use an USB channel, as
I/F alternative. Hence, the CP5-GLAM as a carrier for up to three cards
(2 x PCI Express Mini Card, 1 x ExpressCard) must provide three PCIe lanes,
and three USB ports. Another two USB ports are required for the
USB SSD (Solid State Drive) modules.
The PCI Express circuitry on the CP5-GLAM is comprised of two main components,
a PCI to PCI Express reverse bridge, and a PCI Express packet switch to expand
a single PCIe lane to the required three PCIe lanes, completed by a PCIe clock generator.
The on-board PCI to USB 2.0 host controller (root hub) provides five downstream
facing USB ports, which are shared by two OHCI and one EHCI controller cores.
The CompactPCI interface of the CP5-GLAM J1 connector is wired to a PCI to PCI
bridge, in order to separate the local PCI bus, with its two local PCI
devices, from the external CPCI backplane, which specifies only a single
PCI load for any CompactPCI card.
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In addition to the CompactPCI supply voltages +5V and +3.3V, the CP5-GLAM is
equipped with switching regulators for 1.5V and 1.0V. A power sequencing
controller is in charge of ramping up/down the power rails to the particular
ICs. A front panel bicolor LED indicator reflects the current status
(red = ramp up/down, green = power up finished). Another power controller IC is
dedicated solely to the ExpressCard slot, for hot plug support.
The CP5-GLAM operates as a 32-bit PCI device at 33MHz on the CompactPCI backplane,
resulting in a maximum (theoretic) data transfer rate of 132MByte/s.
Obviously this throughput cannot be sufficient to establish simultaneously a
PCI Express link (2 x 2.5GBit/s), and an USB high speed controller (480Mbit/s),
at full data rate. For ExpressCards or Mini Cards with high throughput such as
an SATA or Gigabit Ethernet controller, or Turbo Memory, some degradation in
speed must be accepted, especially if all card sockets are in use. However,
most data transfers are block or package transfers, with a short burst, and
longer intervals w/o data, so that many applications will not suffer
noticeable from the PCI bottleneck.
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